I2C
Two shared wires, 7-bit addresses, and an acknowledge after every byte.
Reading a sensor register
A classic transaction: ask an MPU-6050 motion sensor for its WHO_AM_I register. Watch START, the address, the ACK bits, the repeated START, and the data coming back.
Whole frame
One transaction: write the register number, turn around with a repeated START, read one byte, and say STOP. 36 clock pulses for a single byte of useful data: the price of addressing and acknowledgement.
START
SDA falls while SCL stays high. Normally SDA only changes while SCL is low, so this one forbidden-looking edge is the unique signal that means 'a transfer begins'.
Address 0x68
The 7-bit device address 0x68 (MPU-6050), most significant bit first. Every device on the bus hears it; only the one that owns this address answers. Address 0x68 followed by the R/W bit makes the byte 0xD0.
R/W = 0 (write)
0 means the master will write: the next byte, the register number, flows from master to slave.
ACK (slave)
On the ninth clock the slave pulls SDA low: 'yes, I am here'. An ACK is a 0. If nobody answers, SDA stays high (pulled up) and the master knows the address is wrong or the device is missing.
Register 0x75 (WHO_AM_I)
The master sends the register number it wants to read. 0x75 is MPU-6050's WHO_AM_I register, which holds the chip's own address, 0x68. The chip stores this as its internal pointer.
Data 0x68 (from slave)
Now the slave drives SDA and the master only clocks. The register holds 0x68, so the chip answers with its own address: the classic WHO_AM_I check that proves the wiring works.
NACK (master)
After the last byte the master leaves SDA high: NACK means 'that was enough, no more'. If it ACKed instead, the slave would send the next register.
Overview
I2C (Inter-Integrated Circuit) connects many chips with just two wires: SCL (clock) and SDA (data). Every device has a 7-bit address; the master starts a transfer, sends an address, and only the matching device answers. After each byte the receiver sends one acknowledge bit.
Both wires are open-drain with pull-up resistors, which is what lets many devices share them safely. Data bits change only while SCL is low and are read while SCL is high. The one exception, START and STOP, is how the bus marks the beginning and end of a transfer.
Key facts
- Wires
- SCL, SDA
- Clock
- Master drives SCL
- Typical speeds
- 100 kHz / 400 kHz / 1 MHz
- Address
- 7 bits (10-bit option)
- Bit order
- MSB first
- Topology
- Multi-master, multi-slave bus
Where you meet it
- Sensors: temperature, IMUs, pressure, light
- Small OLED displays, RTC clocks, EEPROMs, GPIO expanders
- PMBus and SMBus (power management) are close relatives
Watch out for
- Pull-up resistors are mandatory (typically 2.2–10 kΩ). Without them the lines never go high and nothing works.
- Datasheets sometimes quote the 8-bit address (0xD0) and sometimes the 7-bit one (0x68). Mixing them up is the usual 'device not found'.
- A device that holds SCL low (clock stretching) can freeze the bus if the master does not wait for it.
- All devices on the bus must have different addresses. Two identical sensors need an address pin or an I2C multiplexer.
Standards
- NXP UM10204: I2C-bus specification and user manual
- InvenSense MPU-6000/6050 register map