SPI
Four wires, a shared clock, and data moving both ways at once.
Reading a flash chip's ID
A real transaction: send command 0x9F and read back three ID bytes. Switch the SPI mode to see where the clock idles and which edge samples the data.
Whole frame
One CS-low period moved 4 bytes in each direction at the same time: 32 clock cycles. In mode 0 the receiver samples on the rising edge. Master and slave must agree on the mode, or every bit is read one edge off.
CS goes low
The master pulls Chip Select (CS, active low) down. That wakes exactly one device; every other device on the shared SCK/MOSI/MISO lines keeps ignoring the traffic. There is no address in SPI: the wire you pull selects the chip.
Command 0x9F (MOSI)
The master shifts out 0x9F on MOSI, most significant bit first. For many SPI flash chips 0x9F means 'Read JEDEC ID'. While this byte goes out, MISO carries nothing useful.
Manufacturer 0xEF (MISO)
SPI is full duplex: to read a byte the master must send one. It sends dummy 0x00 on MOSI just to make the clock tick, and the flash answers 0xEF on MISO. 0xEF is Winbond's manufacturer ID.
Memory type 0x40 (MISO)
The second ID byte: the device family (0x40 = SPI NOR flash in the Winbond W25Q series). The master again clocks out a dummy byte.
Capacity 0x18 (MISO)
The third ID byte encodes capacity as a power of two: 0x18 = 24, so 2^24 bytes = 16 MiB (W25Q128, 128 Mbit).
Overview
SPI (Serial Peripheral Interface) is a synchronous bus: the master drives a clock (SCK) and, on every clock cycle, one bit leaves on MOSI and one bit arrives on MISO. Because the clock is explicit there are no start or stop bits and speeds of tens of MHz are routine.
There is no addressing and no acknowledgement. Each device gets its own Chip Select line; the master pulls one low to talk to it. What the bytes mean is defined entirely by the device's datasheet.
Key facts
- Wires
- SCK, MOSI, MISO, CS#
- Clock
- Master drives SCK
- Typical speeds
- 1 – 50 MHz
- Bit order
- MSB first (usually)
- Modes
- 0, 1, 2, 3 (CPOL, CPHA)
- Topology
- 1 master, N slaves (1 CS each)
Where you meet it
- Flash memory, SD cards (SPI mode), EEPROMs
- Displays (OLED, TFT, e-paper) and LED drivers
- ADCs/DACs, IMUs, and radio chips such as nRF24 and LoRa modules
Watch out for
- Mode mismatch is the number-one SPI bug: if CPOL/CPHA differ from the datasheet, data is sampled one edge early or late and you read shifted garbage.
- To read, you must write: the master has to clock out dummy bytes to receive data.
- Releasing CS ends the transaction. Raising it between bytes of one command usually aborts the command.
- Slaves with CS high must leave MISO floating (high-Z), otherwise two devices fight over the line.
Standards
- Motorola M68HC11 Reference Manual (SPI)
- Winbond W25Q128 datasheet (JEDEC ID)