HDMI
Video, audio and a conversation on one cable: TMDS pixels, EDID, InfoFrames.
Pixels become TMDS symbols
Eight-bit colour values go in, ten-bit symbols come out, one per channel per pixel clock.
Whole frame
Each pixel clock, three 10-bit symbols leave in parallel: one per colour channel. Eight bits go in, ten come out: the extra two bits buy a signal with few transitions (less interference) and balanced ones and zeros (so it can be AC-coupled).
| Field | Offset | Example value | Meaning |
|---|---|---|---|
| Pixel 0 · Channel 0 (Blue) | Word 0 | 0x00 → 0100000000 | Input 0x00 = 00000000 has 0 ones. Step 1 (fewer transitions): chain the bits with XOR, giving the 9-bit value 100000000 (the top bit records which was used). Step 2 (DC balance): the low 8 bits are sent as they are and a 10th bit records that. Result 0100000000. Running disparity of this channel is now -8. |
| Pixel 0 · Channel 1 (Green) | Word 1 | 0x80 → 0110000000 | Input 0x80 = 10000000 has 1 ones. Step 1 (fewer transitions): chain the bits with XOR, giving the 9-bit value 110000000 (the top bit records which was used). Step 2 (DC balance): the low 8 bits are sent as they are and a 10th bit records that. Result 0110000000. Running disparity of this channel is now -6. |
| Pixel 0 · Channel 2 (Red) | Word 2 | 0xFF → 1000000000 | Input 0xFF = 11111111 has 8 ones. Step 1 (fewer transitions): more than four 1s, so chain the bits with XNOR, giving the 9-bit value 011111111 (the top bit records which was used). Step 2 (DC balance): the low 8 bits are inverted to keep the line's running balance near zero and a 10th bit records that. Result 1000000000. Running disparity of this channel is now -8. |
| Pixel 1 · Channel 0 (Blue) | Word 3 | 0x80 → 1101111111 | Input 0x80 = 10000000 has 1 ones. Step 1 (fewer transitions): chain the bits with XOR, giving the 9-bit value 110000000 (the top bit records which was used). Step 2 (DC balance): the low 8 bits are inverted to keep the line's running balance near zero and a 10th bit records that. Result 1101111111. Running disparity of this channel is now +0. |
| Pixel 1 · Channel 1 (Green) | Word 4 | 0x80 → 1101111111 | Input 0x80 = 10000000 has 1 ones. Step 1 (fewer transitions): chain the bits with XOR, giving the 9-bit value 110000000 (the top bit records which was used). Step 2 (DC balance): the low 8 bits are inverted to keep the line's running balance near zero and a 10th bit records that. Result 1101111111. Running disparity of this channel is now +2. |
| Pixel 1 · Channel 2 (Red) | Word 5 | 0x80 → 1101111111 | Input 0x80 = 10000000 has 1 ones. Step 1 (fewer transitions): chain the bits with XOR, giving the 9-bit value 110000000 (the top bit records which was used). Step 2 (DC balance): the low 8 bits are inverted to keep the line's running balance near zero and a 10th bit records that. Result 1101111111. Running disparity of this channel is now +0. |
| Pixel 2 · Channel 0 (Blue) | Word 6 | 0xFF → 1000000000 | Input 0xFF = 11111111 has 8 ones. Step 1 (fewer transitions): more than four 1s, so chain the bits with XNOR, giving the 9-bit value 011111111 (the top bit records which was used). Step 2 (DC balance): the low 8 bits are inverted to keep the line's running balance near zero and a 10th bit records that. Result 1000000000. Running disparity of this channel is now -8. |
| Pixel 2 · Channel 1 (Green) | Word 7 | 0x80 → 0110000000 | Input 0x80 = 10000000 has 1 ones. Step 1 (fewer transitions): chain the bits with XOR, giving the 9-bit value 110000000 (the top bit records which was used). Step 2 (DC balance): the low 8 bits are sent as they are and a 10th bit records that. Result 0110000000. Running disparity of this channel is now -4. |
| Pixel 2 · Channel 2 (Red) | Word 8 | 0x00 → 0100000000 | Input 0x00 = 00000000 has 0 ones. Step 1 (fewer transitions): chain the bits with XOR, giving the 9-bit value 100000000 (the top bit records which was used). Step 2 (DC balance): the low 8 bits are sent as they are and a 10th bit records that. Result 0100000000. Running disparity of this channel is now -8. |
Overview
HDMI carries uncompressed video and audio from a source to a display. Pixels travel on three differential TMDS data channels plus a clock, each pixel clock sending one 10-bit symbol per channel. Between lines and frames the same wires carry control symbols and 'data islands' with audio and small descriptive packets called InfoFrames.
Alongside the fast wires are slow ones that do the talking: DDC (an I2C bus) lets the source read the display's EDID, HPD signals that a display is present, CEC links remote controls, and HDCP authenticates for copy protection. HDMI 2.1 replaces TMDS with Fixed Rate Link for up to 48 Gbit/s.
Key facts
- Video link
- 3 TMDS data lanes + clock (2.1: FRL)
- Encoding
- TMDS 8b→10b per pixel clock
- Rates
- 1.4: 10.2G · 2.0: 18G · 2.1: 48G bit/s
- Side channels
- DDC (I2C), CEC, HPD, +5V
- EDID
- 128-byte blocks at I2C 0x50
- Compatibility
- DVI-compatible video (same TMDS)
Control, preamble, guard, video
How the receiver knows when pixels begin: periods announced by preambles and bracketed by guard bands.
Whole frame
HDMI interleaves three kinds of period on the same wires: control (syncs), data islands (audio, InfoFrames) and video. Each is announced by a preamble and bracketed by guard bands, so the receiver always knows which it is in.
| Field | Offset | Example value | Meaning |
|---|---|---|---|
| Control period: idle | Word 0–2 | HSYNC=0 VSYNC=0, CTL=0000 | Between pixels, TMDS sends control symbols instead of data: four special 10-bit codes that stand for the 2-bit values 00, 01, 10 and 11. They have many transitions on purpose, so they can never be mistaken for pixel data. Channel 0 carries HSYNC and VSYNC (here both 0), channels 1 and 2 carry four more control bits (CTL0-3). |
| Control period: HSYNC | Word 3–5 | HSYNC=1 | Horizontal sync is not a separate wire: it is encoded in channel 0's control symbol. When HSYNC = 1, channel 0 sends 0010101011 instead of 1101010100. |
| Video preamble | Word 6–8 | CTL0-3 = 1000 | Just before video starts, CTL0-3 = 1000 (channel 1 changes its control symbol) for eight pixel clocks. This announces 'video data period follows'. A data island would be announced by 1010 instead. Shown once; the real preamble lasts 8 clocks. |
| Video guard band | Word 9–11 | guard band | Two pixel clocks of a fixed pattern (here once): 1011001100 / 0100110011 / 1011001100. It marks exactly where the first pixel starts, even if the preamble was damaged. Real HDMI sends 2 guard clocks before video. |
| Pixel 0 (orange) | Word 12–14 | 0100000000 0110000000 1000000000 | R = 255, G = 128, B = 0 encoded as three TMDS symbols (see the previous scene). Running disparity restarts from 0 at the beginning of each video period. |
| Pixel 1 (gray) | Word 15–17 | 1101111111 1101111111 1101111111 | R = G = B = 128. Equal values in the three channels give the same symbol on each, though the running balance can make later ones differ. |
An AVI InfoFrame
A tiny packet in the data island that describes the picture, with a real checksum.
Whole frame
82 02 0D A7 10 A8 00 10 00 00 00 00 00 00 00 00 00: a 17-byte note that tells the TV what the picture is: RGB, BT.709, 16:9, format number 16. The TV reads it every frame, so it follows mode changes instantly.
| Field | Offset | Example value | Meaning |
|---|---|---|---|
| Packet type | Byte 0 | 0x82 = AVI InfoFrame | InfoFrames are small descriptive packets sent in the data islands. 0x82 = AVI (Auxiliary Video Information); 0x84 = audio; 0x81 = vendor specific. |
| Version | Byte 1 | 2 | The layout version of this packet type. Version 2 is the common one for AVI. |
| Length | Byte 2 | 13 | Bytes of data after the checksum: 13. |
| Checksum | Byte 3 | 0xA7 (sum ≡ 0) | Chosen so that the sum of every byte of the InfoFrame (header, checksum and data) is 0 modulo 256. Computed for real here: the sum is 0. A sink ignores an InfoFrame whose sum is not 0. |
| Data byte 1: format | Byte 4 | RGB, active format valid | Colour format and whether the picture has borders. |
| Data byte 2: colorimetry and aspect | Byte 5 | BT.709, 16:9 | How to interpret the colours and the shape of the picture. |
| Data byte 3: range and scaling | Byte 6 | defaults | Extended colorimetry, quantization range (full or limited), and whether the picture was scaled. All defaults here. |
| VIC | Byte 7 | 16 = 1080p60 | Video Identification Code: a number from the CTA-861 table that names the whole video format in one byte. 16 = 1920×1080 progressive at 60 Hz. Others: 4 = 720p60, 5 = 1080i60, 31 = 1080p50, 97 = 3840×2160p60. |
| Data byte 5 | Byte 8 | 0 | YCC quantization range, content type, and pixel repetition (low-resolution modes are sent with each pixel repeated). 0 = none. |
| Bar information | Byte 9–16 | none | Positions of black bars, if the first byte said there are any. Unused here. |
EDID: the display's identity
What the TV tells the source over the DDC wires when it is plugged in.
Whole frame
The TV's identity card: who made it, how big it is, which colours it can show and which old modes it understands. The block ends with a checksum byte so that all 128 bytes sum to 0.
| Field | Offset | Example value | Meaning |
|---|---|---|---|
| Header | Byte 0–7 | 00 FF FF FF FF FF FF 00 | A fixed 8-byte pattern: 00, six FF, 00. It is how a reader recognises an EDID block at all. |
| Manufacturer ID | Byte 8–9 | "DEM" | Three letters packed 5 bits each (A = 1): 'DEM' here, a made-up demo ID. Real IDs are assigned by UEFI (SAM = Samsung, DEL = Dell, GSM = LG). |
| Product code | Byte 10–11 | 0x1234 | The maker's model number. Note that multi-byte numbers in EDID are little-endian: 34 12 means 0x1234. |
| Serial number | Byte 12–15 | 1 | A 32-bit number (little-endian), often unused. |
| Week of manufacture | Byte 16 | 12 | Week 1–54 of the year. |
| Year of manufacture | Byte 17 | 34 → 2024 | Years since 1990. |
| EDID version | Byte 18 | 1 | EDID 1.3 here (1.4 adds more). The version and revision are two bytes. |
| EDID revision | Byte 19 | 3 | 3 = revision 3. |
| Video input | Byte 20 | 0x80 = digital | Bit 7 = 1 means a digital input (HDMI/DVI/DisplayPort); the lower bits describe the interface. |
| Width | Byte 21 | 51 cm | Physical screen width in centimetres. |
| Height | Byte 22 | 29 cm | Physical screen height in centimetres. Together with the resolution, software computes DPI. |
| Gamma | Byte 23 | 2.20 | Stored as (gamma × 100) − 100: 0x78 = 120 → 2.20. |
| Features | Byte 24 | sRGB, preferred timing | Power-management modes, colour type, 'sRGB is the default colour space' and 'the first detailed timing is the preferred mode'. |
| Chromaticity | Byte 25–34 | sRGB primaries | The CIE xy coordinates of the red, green and blue primaries and the white point, 10 bits each, packed into 10 bytes. These are the sRGB values, so a source can map colours correctly. |
| Established timings | Byte 35–37 | VGA, SVGA, XGA | A bitmap of old, standard modes supported: here 640×480@60, 800×600@60 and 1024×768@60. |
| Standard timings | Byte 38–53 | 1080p60, 720p60 | Eight 2-byte entries. Each gives horizontal pixels as (value+31)×8, an aspect ratio and a refresh rate offset. D1 40 = (209+31)×8 = 1920 wide, 16:9, 60 Hz = 1920×1080@60; 81 40 = 1280×720@60. 01 01 means unused. |
EDID: the preferred video mode
One 18-byte descriptor defines a complete 1080p60 mode.
Whole frame
02 3A 80 18 71 38 2D 40 58 2C 45 00 FD 1E 11 00 00 1E: 148.5 MHz ÷ (2200 × 1125) = 60.00 Hz. The whole video mode is described by a handful of numbers, and these 18 bytes are what the TV says it prefers.
| Field | Offset | Example value | Meaning |
|---|---|---|---|
| Pixel clock | Byte 0–1 | 14850 × 10 kHz = 148.50 MHz | In units of 10 kHz, little-endian: 0x3A02 = 14,850 → 148.50 MHz. Every pixel of the whole frame, including blanking, is sent at this rate. |
| Horizontal active / blanking | Byte 2–4 | 1920 + 280 = 2200 | Two 12-bit numbers squeezed into 3 bytes: the low 8 bits of each, then both high nibbles in the third byte. Active = 0x780 = 1920 pixels; blanking = 0x118 = 280 pixels. Total per line: 2200 clocks. |
| Vertical active / blanking | Byte 5–7 | 1080 + 45 = 1125 | The same packing for lines: active = 0x438 = 1080 lines; blanking = 0x02D = 45 lines. Total 1125 lines per frame. |
| Sync timing | Byte 8–11 | H 88/44 · V 4/5 | Where the sync pulses sit inside the blanking: horizontal front porch 88 and pulse width 44 (clocks); vertical front porch 4 and pulse width 5 (lines). The top 2 bits of each are in the last byte. |
| Image size | Byte 12–14 | 509 × 286 mm | Physical size in millimetres: 509 × 286 mm (a 23-inch panel). Low bytes first, then a byte with both high nibbles. |
| Borders | Byte 15–16 | 0, 0 | Overscan border in pixels (horizontal, vertical): 0. |
| Flags | Byte 17 | 0x1E | 0x1E: digital separate sync, positive polarity for both vertical and horizontal sync, progressive scan. |
Plugging in
The conversation before the first pixel.
Whole exchange
Before a single pixel moves, HDMI is a conversation: detect, ask what you can show, agree a mode, then stream. Most 'no signal' problems happen in the first three steps.
1Hot Plug Detect
The TV raises the Hot Plug Detect line (using the 5 V the source supplies). To the source this means 'a display is connected and ready'.
2Reading the EDID
The source reads 128+ bytes over the DDC wires, which are an ordinary I2C bus (see the I2C page). The TV's EDID memory lives at address 0x50. The bytes are the ones in the EDID scenes above.
3Setting up the link (HDMI 2.0)
For fast modes the source configures the sink over I2C address 0x54 (the Status and Control Data Channel): turn on scrambling and set the clock ratio. Slow modes skip this.
4Video starts flowing
The source picks the best mode that both sides support (usually the preferred timing from the EDID), starts the TMDS clock and sends video, with an AVI InfoFrame in each frame's data islands to say what the picture is.
5Copy-protection handshake
For protected content the source authenticates the sink over the same DDC wires and then encrypts the video. If this fails you see a black or noisy picture while the plain mode works fine.
6A remote-control message
On a separate single wire, CEC (Consumer Electronics Control) lets devices control each other. 0x36 is 'Standby': this is how one remote switches the whole system off.
Where you meet it
- TVs, monitors, projectors, game consoles, set-top boxes, laptops
- Capture cards and HDMI-to-USB or HDMI-to-NDI converters in streaming setups
- Audio return (ARC / eARC) from a TV to a soundbar over the same cable
Watch out for
- A black screen on first connection is often an EDID or HDCP problem, not a cable fault: try another port, another cable, or an EDID emulator.
- Bandwidth is a budget: 4K60 4:4:4 at 8-bit needs HDMI 2.0's 18 Gbit/s; 4K120 or 10-bit needs 2.1 or chroma subsampling (4:2:0).
- Long passive cables fail at high rates before they fail at low ones, so the same cable can work at 1080p and not at 4K.
- Switches and splitters sit between HDCP and EDID: a cheap splitter that shows only the lowest common EDID will limit everything to its weakest display.
Standards
- HDMI Specification 1.4b / 2.0 / 2.1 (HDMI Forum)
- DVI 1.0 (Digital Display Working Group): TMDS
- VESA E-EDID 1.4
- CTA-861 (InfoFrames, VICs)